Result 1 to 20 of 264 total
Emulating transactional memory on FPGA multiprocessors. (English)
Berekovic, Mladen (ed.) et al., Architecture of computing systems ‒ ARCS 2011. 24th international conference, Como, Italy, February 24‒25, 2011. Proceedings. Berlin: Springer (ISBN 978-3-642-19136-7/pbk). Lecture Notes in Computer Science 6566, 74-85 (2011).
1
Floorplacement for partial reconfigurable FPGA-based systems. (English)
Int. J. Reconfig. Comput. 2011, Article ID 483681, 12 p. (2011).
2
Island-based adaptable embedded system design (English)
Embedded Systems Letters 3, No. 2, 53-57 (2011).
3
Interorganisational systems within smes aggregations: an exploratory study on information requirements of an industrial district (English)
IJITM 10, No. 2-4, 208-232 (2011).
4
Applying dynamic reconfiguration in the mobile robotics domain: A case study on computer vision algorithms (English)
TRETS 4, No. 3, 29 (2011).
5
Dedicated hardware accelerators for the epistatic analysis of human genetic data (English)
ICSAMOS, 102-109 (2011).
6
A hybrid mapping-scheduling technique for dynamically reconfigurable hardware (English)
FPL, 177-180 (2011).
7
Emulating transactional memory on FPGA multiprocessors (English)
ARCS, 74-85 (2011).
8
Rebit: A tool to manage and analyse FPGA-based reconfigurable systems (English)
IPDPS Workshops, 220-227 (2011).
9
An efficient quantum-dot cellular automata adder (English)
DATE, 1220-1223 (2011).
10
A design methodology to implement memory accesses in high-level synthesis (English)
CODES+ISSS, 49-58 (2011).
11
Decision-theoretic design space exploration of multiprocessor platforms. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 7, 1083-1095 (2010).
12
Ant colony heuristic for mapping and scheduling tasks and communications on heterogeneous embedded systems. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 6, 911-924 (2010).
13
io-port 50152259 Bertels, Koen;
Sima, Vlad Mihai;
Yankova, Yana;
Kuzmanov, Georgi;
Luk, Wayne;
Coutinho, José Gabriel F.;
Ferrandi, Fabrizio;
Pilato, Christian;
Lattuada, Marco;
Sciuto, Donatella;
Michelotti, Andrea
Hartes: hardware-software codesign for heterogeneous multicore platforms (English)
IEEE Micro 30, No. 5, 88-97 (2010).
14
Guest editors’ introduction: special section on system-level design of reliable architectures (English)
IEEE Trans. Computers 59, No. 5, 577-578 (2010).
15
Placement and floorplanning in dynamically reconfigurable fpgas (English)
TRETS 3, No. 4, 24 (2010).
16
Designing and validating access policies to reconfigurable resources in multiprocessor systems on chip (English)
ICSAMOS, 365-371 (2010).
17
Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation (English)
GECCO, 1267-1274 (2010).
18
A compact transactional memory multiprocessor system on FPGA (English)
FPL, 578-581 (2010).
19
A design workflow for dynamically reconfigurable multi-FPGA systems (English)
VLSI-SoC, 414-419 (2010).
20
Result 1 to 20 of 264 total
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