Result 1 to 20 of 97 total
Lifting for conic mixed-integer programming. (English)
Math. Program. 126, No. 2 (A), 351-363 (2011).
1
FPGA architecture for 2D discrete Fourier transform based on 2D decomposition for large-sized data (English)
Signal Processing Systems 64, No. 1, 109-122 (2011).
2
Multidimensional DFT IP generator for FPGA platforms (English)
IEEE Trans. on Circuits and Systems 58-I, No. 4, 755-764 (2011).
3
Exploring gabor filter implementations for visual cortex modeling on FPGA (English)
FPL, 311-316 (2011).
4
Impact of circuit degradation on FPGA design security (English)
ISVLSI, 230-235 (2011).
5
Towards resilient micro-architectures: datapath reliability enhancement using STT-MRAM (English)
ISVLSI, 236-241 (2011).
6
A hardware architecture for accelerating neuromorphic vision algorithms (English)
SiPS, 355-360 (2011).
7
Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores (English)
ISLPED, 247-252 (2011).
8
Mixed constraints for test input generation - an initial exploration (English)
ASE, 548-551 (2011).
9
Enabling architectural innovations using non-volatile memory (English)
ACM Great Lakes Symposium on VLSI, 439-444 (2011).
10
Automated mapping for reconfigurable single-electron transistor arrays (English)
DAC, 878-883 (2011).
11
An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores (English)
DAC, 729-734 (2011).
12
An algorithm-architecture co-design framework for gridding reconstruction using fpgas (English)
DAC, 585-590 (2011).
13
An FPGA implementation of information theoretic visual-saliency system and its optimization (English)
FCCM, 41-48 (2011).
14
A streaming FPGA implementation of a steerable filter for real-time applications (abstract only) (English)
FPGA, 281 (2011).
15
SHARC: A streaming model for FPGA accelerators and its application to saliency (English)
DATE, 1237-1242 (2011).
16
Activity and device position recognition in mobile devices (English)
Ubicomp, 591-592 (2011).
17
Energy-delay performance of nanoscale transistors exhibiting single electron behavior and associated logic circuits. (English)
J. Low Power Electron. 6, No. 3, 415-428 (2010).
18
Conic mixed-integer rounding cuts. (English)
Math. Program. 122, No. 1 (A), 1-20 (2010).
19
On the effects of process variation in network-on-chip architectures (English)
IEEE Trans. Dependable Sec. Comput. 7, No. 3, 240-254 (2010).
20
Result 1 to 20 of 97 total
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