Result 1 to 20 of 22 total
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. (English)
ACM Trans. Archit. Code Optim. 8, No. 2, 6 (2011).
1
Multi-core cache hierarchies (English)
Synthesis Lectures on Computer Architecture: Multi-Core Cache Hierarchies (2011).
2
The role of optics in future high radix switch design (English)
ISCA, 437-448 (2011).
3
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems (English)
ISCA, 425-436 (2011).
4
System implications of memory reliability in exascale computing (English)
SC, 46 (2011).
5
FREE-p: protecting non-volatile memory against both hard and soft errors (English)
HPCA, 466-477 (2011).
6
Rethinking DRAM design and organization for energy-constrained multi-cores (English)
ISCA, 175-186 (2010).
7
Simple but effective heterogeneous Main memory with on-chip memory controller support (English)
SC, 1-11 (2010).
8
Towards scalable, energy-efficient, bus-based on-chip networks (English)
HPCA, 1-12 (2010).
9
Non-uniform power access in large caches with low-swing wires (English)
HiPC, 59-68 (2009).
10
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems (English)
SC (2009).
11
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy (English)
HPCA, 262-274 (2009).
12
Architecting efficient interconnects for large caches with CACTI 6.0. (English)
IEEE Micro 28, No. 01, 69-79 (2008).
13
Architecting efficient interconnects for large caches with CACTI 6.0 (English)
IEEE Micro 28, No. 1, 69-79 (2008).
14
Scalable and reliable communication for hardware transactional memory (English)
PACT, 144-154 (2008).
15
Interconnect design considerations for large NUCA caches (English)
ISCA, 369-380 (2007).
16
Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0 (English)
MICRO, 3-14 (2007).
17
Leveraging wire properties at the microarchitecture level. (English)
IEEE Micro 26, No. 06, 40-52 (2006).
18
Leveraging wire properties at the microarchitecture level (English)
IEEE Micro 26, No. 6, 40-52 (2006).
19
Interconnect-aware coherence protocols for chip multiprocessors (English)
ISCA, 339-351 (2006).
20
Result 1 to 20 of 22 total
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