On-line power optimization of data flow multi-core architecture based on vdd-hopping for local dynamic voltage and frequency scaling. (English)
J. Low Power Electron. 7, No. 2, 265-273 (2011).
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On line power optimization of data flow multi-core architecture based on Vdd-Hopping for local DVFS. (English)
van Leuken, René (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization, and simulation. 20th international workshop, PATMOS 2010, Grenoble, France, September 7‒10, 2010. Revised selected papers. Berlin: Springer (ISBN 978-3-642-17751-4/pbk). Lecture Notes in Computer Science 6448, 94-104 (2011).
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On line power optimization of data flow multi-core architecture based on vdd-hopping for local DVFS (English)
PATMOS, 94-104 (2010).
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Power modeling in systemc at transaction level, application to a DVFS architecture (English)
ISVLSI, 463-466 (2008).
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