Result 21 to 26 of 26 total
FPGA-based efficient design approach for large-size two’s complement squarers (English)
ASAP, 18-23 (2007).
21
Survey of biological high performance computing: algorithms, implementations and outlook research (English)
CCECE, 1926-1929 (2006).
22
An optimized design approach for squaring large integers using embedded hardwired multipliers (English)
AICCSA, 248-254 (2006).
23
Polyphase filter approach for high performance, FPGA-based quadrature demodulation. (English)
J. VLSI Signal Process. Syst. Signal Image Video Technol. 32, No.3, 237-254 (2002).
24
A low power direct digital frequency synthesizer with 60 dbc spectral purity (English)
ACM Great Lakes Symposium on VLSI, 166-171 (2002).
25
Hardware optimized direct digital frequency synthesizer architecture with 60 dbc spectral purity (English)
ISCAS (5), 361-364 (2002).
26
Result 21 to 26 of 26 total