Result 1 to 20 of 100 total
Accelerating the photon mapping algorithm and its hardware implementation (English)
ASAP, 149-157 (2011).
1
22nd IEEE international conference on application-specific systems, architectures and processors, ASAP 2011, Santa Monica, CA, USA, sept. 11-14, 2011 (English)
ASAP (2011).
2
An efficient method for evaluating complex polynomials. (English)
J. Signal Process. Syst. Signal Image Video Technol. 58, No. 1, 17-27 (2010).
3
Combining leak-resistant arithmetic for elliptic curves defined over $F_{p}$ and RNS representation (English)
IACR Cryptology ePrint Archive 2010, 311 (2010).
4
An efficient method for evaluating complex polynomials (English)
Signal Processing Systems 58, No. 1, 17-27 (2010).
5
Design of high-throughput fixed-point complex reciprocal/square-root unit (English)
IEEE Trans. on Circuits and Systems 57-II, No. 8, 627-631 (2010).
6
Implementing decimal floating-point arithmetic through binary: some suggestions (English)
ASAP, 317-320 (2010).
7
Exploration of power-delay trade-offs with heterogeneous adders by integer linear programming. (English)
J. Circuits Syst. Comput. 18, No. 4, 787-800 (2009).
8
A radix-8 complex divider for FPGA implementation (English)
FPL, 236-241 (2009).
9
Design and implementation of a radix-4 complex division unit with prescaling (English)
ASAP, 83-90 (2009).
10
Digital arithmetic (English)
Wiley Encyclopedia of Computer Science and Engineering (2008).
11
An efficient method for evaluating polynomial and rational function approximations (English)
ASAP, 233-238 (2008).
12
Complex square root with operand prescaling. (English)
J. VLSI Signal Process. Syst. Signal Image Video Technol. 49, No. 1, 19-30 (2007).
13
The art of deception: adaptive precision reduction for area efficient physics acceleration (English)
MICRO, 394-406 (2007).
14
A hardware-oriented method for evaluating complex polynomials (English)
ASAP, 122-127 (2007).
15
A design method for heterogeneous adders (English)
ICESS, 121-132 (2007).
16
High-Performance Low-Power Left-to-Right Array Multiplier Design. (English)
IEEE Transactions on Computers 54, No.03, 272-283 (2005).
17
High-radix logarithm with selection by rounding: Algorithm and implementation. (English)
J. VLSI Signal Process. 40, No. 1, 109-123 (2005).
18
High-performance low-power left-to-right array multiplier design (English)
IEEE Trans. Computers 54, No. 3, 272-283 (2005).
19
Variable radix real and complex digit-recurrence division (English)
ASAP, 316-321 (2005).
20
Result 1 to 20 of 100 total
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