Result 1 to 20 of 50 total
Topological properties of Hierarchical Interconnection Networks: a review and comparison. (English)
J. Electr. Comput. Eng. 2011, Article ID 189434, 12 p. (2011).
1
Topological properties of hierarchical interconnection networks: A review and comparison (English)
J. Electrical and Computer Engineering 2011 (2011).
2
Topological network design: A survey. (English)
J. Netw. Comput. Appl. 32, No. 3, 501-509 (2009).
3
The use of multiple connected pseudo minterms in the synthesis of MVL functions (English)
ISMVL, 145-150 (2009).
4
Knowledge based document management system for free-text documents discovery. (English)
J. Comb. Math. Comb. Comput. 67, 141-152 (2008).
5
An efficient representation of Benes networks and its applications. (English)
J. Discrete Algorithms 6, No. 1, 11-19 (2008).
6
Corrections to "design and performance analysis of a unified, reconfigurable HMAC-hash unit" [Dec 07 2683-2695] (English)
IEEE Trans. on Circuits and Systems 55-I, No. 2, 708 (2008).
7
Design and analysis of a fault tolerant hybrid mobile scheme. (English)
Inf. Sci. 177, No. 12, 2602-2620 (2007).
8
Design and analysis of reliable and fault-tolerant computer systems. (English)
Hackensack, NJ: World Scientific (ISBN 1-86094-668-2/hbk; 978-1-86094-890-9/ebook). xxi, 440~p. \sterling~56.00; \$~98.00/hbk (2007).
9
Design and analysis of reliablle and fault-tolerant computer systems (English)
Design and analysis of reliablle and fault-tolerant computer systems, I-XXI, 1-440 (2007).
10
Knowledge discovery using neural network (English)
IKE, 432-438 (2007).
11
Weighted and ordered direct cover algorithms for minimization of MVL functions (English)
ISMVL, 48 (2007).
12
An FPGA design of a unified hash engine for ipsec authentication (English)
IWSOC, 450-453 (2005).
13
Iterative-based minimization of unary 4-valued functions for current-mode CMOS realization (English)
ISMVL, 315-320 (2004).
14
A modified ant colony algorithm for evolutionary design of digital circuits (English)
IEEE Congress on Evolutionary Computation (1), 708-715 (2003).
15
Digital circuit design through simulated evolution (SimE) (English)
IEEE Congress on Evolutionary Computation (1), 375-381 (2003).
16
Fault tolerance in topological optimization of computer networks (English)
Computers and Their Applications, 84-87 (2003).
17
Enumerative techniques in topological optimization of computer networks subject to fault tolerance and reliability (English)
IASTED PDCS, 123-128 (2002).
18
A hybrid scheme for tolerating mobile support station failures (English)
ISCA PDCS, 436-441 (2001).
19
A new improved cost-table-based technique for synthesis of 4-valued unary functions implemented using current-mode CMOS circuits (English)
ISMVL, 15-20 (2001).
20
Result 1 to 20 of 50 total
Start
Contact
Print
General Help
