Result 1 to 20 of 49 total
An FPGA softcore based implementation of a bird call recognition system for sensor networks (English)
DASIP, 1-6 (2010).
1
System requirements for industrial wireless sensor networks (English)
ETFA, 1-8 (2010).
2
Guest editorial CAPA’08 configurable computing: configuring algorithms, processes, and architecture issue II: Configuring hardware architecture. (English)
ACM Trans Embed. Comput. Syst. 9, No. 2 (2009).
3
Guest editorial CAPA’08 configurable computing: configuring algorithms, processes, and architecture issue I: Configuring algorithms and processes. (English)
ACM Trans Embed. Comput. Syst. 9, No. 1 (2009).
4
Design exploration for FPGA-based multiprocessor architecture: JPEG encoding case study (English)
FCCM, 299-302 (2009).
5
An ILP formulation for architectural synthesis and application mapping on FPGA-based hybrid multi-processor SOC (English)
FPL, 451-454 (2008).
6
A web server based edge detector implementation in FPGA (English)
ISVLSI, 441-446 (2008).
7
System level design methodology for hybrid multi-processor soc on FPGA (English)
FCCM, 312-313 (2008).
8
Dynamically reconfigurable architectures (English)
EURASIP J. Emb. Sys. 2007 (2007).
9
A hybrid reconfigurable cluster-on-chip architecture with message passing interface for image processing applications (English)
FPL, 609-612 (2007).
10
QUKU: A FPGA based flexible coarse grain architecture design paradigm using process networks (English)
IPDPS, 1-7 (2007).
11
Operating system integration and performance of a multi stream cipher architecture for reconfigurable system-on-chip (English)
FCCM, 283-284 (2007).
12
Automatic self-reconfiguration of system-on-chip peripherals (English)
FCCM, 313-316 (2007).
13
A Process Model for Hardware Modules in Reconfigurable System-on-Chip. (German)
Karl, Wolfgang et al., ARCS’06, 19th International Conference on Architecture of Computing Systems, Workshop Proceedings, March 16 2006, Frankfurt am Main. Bonner Köllen Verlag (ISBN 3-88579-175-7). GI-Edition - Lecture Notes in Informatics (LNI), P-81, 205-214 (2006).
14
Multi stream cipher architecture for reconfigurable system-on-chip (English)
FPL, 1-4 (2006).
15
QUKU: A two-level reconfigurable architecture (English)
ISVLSI, 109-116 (2006).
16
A process model for hardware modules in reconfigurable system-on-chip (English)
ARCS Workshops, 205-214 (2006).
17
QUKU: A coarse grained paradigm for fpgas (English)
Dynamically Reconfigurable Architectures (2006).
18
A reconfigurable cluster-on-chip architecture with MPI communication layer (English)
FCCM, 351-352 (2006).
19
VPN acceleration using reconfigurable system-on-chip technology (English)
FCCM, 281-282 (2006).
20
Result 1 to 20 of 49 total
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