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Derivation of reduced test vectors for bit-parallel multipliers over $GF(2^m)$. (English)
IEEE Trans. Comput. 57, No. 09, 1289-1294 (2008).
Summary: This paper presents an algebraic testing method for detecting stuck-at faults in the polynomial basis (PB) bit parallel (BP) multiplier circuits over $GF(2m)$. The proposed technique derives the test vectors from the expressions of the inner product (IP) variables without any requirement of ATPG tool. This low complexity testing method requires (2m+1) test vectors for detect-ing single stuck-at faults in the AND part and multiple stuck-at faults in EXOR part of the multiplier circuits. The test vectors are independent of multiplier’s structure proposed in [11] but dependant on m. For the multiplier circuits, the test set is found to be smaller in size than the ATPG-generated test set. The test set provides 100\% single stuck-at fault coverage.
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