Summary: \BeginparAs the gap between processor and memory speeds continues to widen, methods for evaluating memory system designs before they are implemented in hardware are becoming increasingly important. One such method, trace-driven memory simulation, has been the subject of intense interest among researchers and has, as a result, enjoyed rapid development and substantial improvements during the past decade. This article surveys and analyzes these developments by establishing criteria for evaluating trace-driven methods, and then applies these criteria to describe, categorize, and compare over 50 trace-driven simulation tools. We discuss the strengths and weaknesses of different approaches and show that no single method is best when all criteria, including accuracy, speed, memory, flexibility, portability, expense, and ease of use are considered. In a concluding section, we examine fundamental limitations to trace-driven simulation, and survey some recent developments in memory simulation that may overcome these bottlenecks.\Endpar (Provider: ACM) Review: \BeginparThe authors survey and summarize trace-driven methodologies for the performance evaluation of (mainly uniprocessor) memory systems. Techniques for trace collection, reduction, and processing are described. Based on criteria such as accuracy, speed, overhead, and portability, many tools are assessed comprehensively.\Endpar \BeginparAs a survey, this paper is informative for those who are interested in using trace-driven simulations to evaluate their designs and for those who are working in or planning to work in this area. The authors have also done a good job of identifying important issues for each stage of simulations.\Endpar \BeginparThe paper may be difficult to read for those who are not familiar with the subject. Also, the authors{’} discussion of future research on this subject may fall short. As they point out in the conclusion, today{’}s microprocessors are more complex, with features such as out-of-order execution, prefetching, superscalar processing, and multiple levels of inclusive or noninclusive caches, which may be nonblocking or sub-blocked. It is not clear whether direct application of the current methodology and tools will produce accurate results.\Endpar (Provider: ACM)