Summary: This paper major discusses using Petri net to model the control structure of instructions while branch occur. Branch instructions can reduce the performance of pipelined processors by interrupting the steady flow of instructions into the pipelined one’s. In this paper, we describe a Petri nets based methodology for modeling and evaluation branch control of pipelined processors. A general purpose Petri nets simulator has been developed using trace- driven approach, SES/workbench. Using this simulator, the execution of the Petri nets models of some sub-models have been simulated. In this paper, we only concern on the scheme that makes the Petri nets to model the branch control for pipelined processors, and to compare the performance and cost/performance ratio of the pipelined processors with/without branch target buffer.