id: 05853646
dt: a
an: 05853646
au: Carazo, P.; Apolloni, R.; Castro, F.; Chaver, D.; Pinuel, L.; Tirado, F.
ti: L1 data cache power reduction using a forwarding predictor.
so: van Leuken, René (ed.) et al., Integrated circuit and system design. Power
    and timing modeling, optimization, and simulation. 20th international
    workshop, PATMOS 2010, Grenoble, France, September 7‒10, 2010.
    Revised selected papers. Berlin: Springer (ISBN 978-3-642-17751-4/pbk).
    Lecture Notes in Computer Science 6448, 116-125 (2011).
py: 2011
pu: Berlin: Springer
la: EN
cc: 
ut: 
ci: 
li: doi:10.1007/978-3-642-17752-1_12
ab: Summary: In most modern processor designs the L1 data cache has become a
    major consumer of power due to its increasing size and high frequency
    access rate. In order to reduce this power consumption, we propose in
    this paper a straightforward filtering technique. The mechanism is
    based on a highly accurate forwarding predictor that determines if a
    load instruction will take its corresponding data via forwarding from
    the load-store structure ‒ thus avoiding the data cache access ‒ or
    it should catch it from the data cache. Our simulation results show
    that 36\% data cache power savings can be achieved on average, with a
    negligible performance penalty of 0.1\%.
rv: