Result 1 to 20 of 82 total
Real-time embedded emotional controller. (English)
Neural Comput. Appl. 19, No. 1, 13-19 (2010).
1
EDXY - A low cost congestion-aware routing algorithm for network-on-chips (English)
Journal of Systems Architecture - Embedded Systems Design 56, No. 7, 256-264 (2010).
2
Test pattern selection and compaction for sequential circuits in an HDL environment (English)
Asian Test Symposium, 53-56 (2010).
3
A reconfigurable online BIST for combinational hardware using digital neural networks (English)
European Test Symposium, 139-144 (2010).
4
A partitioning approach to improve reconfigurable neuron-inspired online BIST (English)
IOLTS, 173-178 (2010).
5
Emotion on FPGA: model driven approach. (English)
Expert Syst. Appl. 36, No. 4, 7369-7378 (2009).
6
Sign bit reduction encoding for low power applications. (English)
J. Signal Process. Syst. Signal Image Video Technol. 57, No. 3, 321-329 (2009).
7
Emotion on FPGA: model driven approach (English)
Expert Syst. Appl. 36, No. 4, 7369-7378 (2009).
8
Sign bit reduction encoding for low power applications (English)
Signal Processing Systems 57, No. 3, 321-329 (2009).
9
Optimizing parametric BIST using bio-inspired computing algorithms (English)
DFT, 268-276 (2009).
10
Online network-on-chip switch fault detection and diagnosis using functional switch faults. (English)
J. UCS 14, No. 22, 3716-3736, electronic only (2008).
11
A selective trigger scan architecture for VLSI testing. (English)
IEEE Trans. Comput. 57, No. 03, 316-328 (2008).
12
A selective trigger scan architecture for VLSI testing (English)
IEEE Trans. Computers 57, No. 3, 316-328 (2008).
13
Enhanced TED: A new data structure for RTL verification (English)
VLSI Design, 481-486 (2008).
14
An noc test strategy based on flooding with power, test time and coverage considerations (English)
VLSI Design, 409-414 (2008).
15
Stall power reduction in pipelined architecture processors (English)
VLSI Design, 541-546 (2008).
16
BARP-A dynamic routing protocol for balanced distribution of traffic in nocs (English)
DATE, 1408-1413 (2008).
17
A novel GA-based high-level synthesis technique to enhance RT-level concurrent testing (English)
IOLTS, 173-174 (2008).
18
Reliability in application specific mesh-based noc architectures (English)
IOLTS, 207-212 (2008).
19
Low test application time resource binding for behavioral synthesis. (English)
ACM Trans. Des. Autom. Electron. Syst. 12, No. 2 (2007).
20
Result 1 to 20 of 82 total
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