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06090004 Loke, Wei Ting Ha, Yajun A routing architecture for FPGAs with dual-VT switch box and logic clusters. Choy, Oliver C. S. (ed.) et al., Reconfigurable computing: Architectures, tools and applications. 8th international symposium, ARC 2012, Hong Kong, China, March 19--23, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-28364-2/pbk). Lecture Notes in Computer Science 7199, 174-186 (2012). 2012 Berlin: Springer EN programmable-$V _{T }$ reverse back bias switch box FPGA

doi:10.1007/978-3-642-28365-9_15

Summary: In this paper, we present a novel routing architecture for FPGAs with dual-$V _{T }$ LUT and switch box architectures. The use of reverse back bias (RBB) is one strategy for mitigating leakage power, a critical issue as process technologies shrink relentlessly towards sub-nano proportions. FPGAs with the ability to adjust fabric $V _{T }$ at configuration time offer leakage power reduction without sacrificing circuit speed. Most of the related works today investigate dual-$V _{T }$ optimizations at the logic cluster level; Altera's Stratix-III/IV line of FPGAs already demonstrate the feasibility of a similar architecture. In this work, we present a further advancement to the dual-$V _{T }$ architecture -- the switch box, and a routing architecture that demonstrates the effectiveness of this true dual-$V _{T }$ fabric architecture. Our switch box advancement alone yields an average of 17.44\% in leakage power savings, and with the full EDA flow an average 29.65\% in total power savings is observed.