Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system (English)
DATE, 1406-1411 (2007).
1
Channel equalization in HSDPA receivers: trade-off between performance and complexity with a variable oversampling (English)
VTC Spring, 2439-2443 (2006).
2
Excess loop delay effects in continuous-time quadrature bandpass sigma-delta modulators (English)
ISCAS (1), 1029-1032 (2003).
3
Design of high speed bipolar si/sige ics for optical wide band communications (English)
ISCAS (2), 496-499 (1999).
4
Active compensation of interconnect losses for multi-GHz clock distribution networks. (English)
IEEE Trans. Circuits Syst., II, Analog Digit. Signal Process. 39, No.11, 790-798 (1992).
5
Multi-gb/s silicon bipolar clock recovery IC (English)
IEEE Journal on Selected Areas in Communications 9, No. 5, 656-663 (1991).
6
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