Result 201 to 220 of 250 total
A logical framework for multi-agent systems and joint attitudes (English)
DAI, 16-30 (1995).
201
Object oriented design for a distributed priority queue (English)
COMPSAC, 192-198 (1995).
202
The elmore delay as a bound for RC trees with generalized input signals (English)
DAC, 364-369 (1995).
203
Simultaneous gate and interconnect sizing for circuit-level delay optimization (English)
DAC, 690-695 (1995).
204
Transmission line synthesis (English)
DAC, 358-363 (1995).
205
Generating sparse partial inductance matrices with guaranteed stability (English)
ICCAD, 45-52 (1995).
206
Coping with $RC(L)$ interconnect design headaches (English)
ICCAD, 246-253 (1995).
207
Constrained multivariable optimization of transmission lines with general topologies (English)
ICCAD, 130-137 (1995).
208
A sequential quadratic programming approach to concurrent gate and wire sizing (English)
ICCAD, 144-151 (1995).
209
A portable parallel N-body solver (English)
PPSC, 331-336 (1995).
210
Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 13, No. 12, 1526-1535 (1994).
211
RICE: Rapid interconnect circuit evaluation using AWE. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 13, No. 6, 763-776 (1994).
212
Time-domain macromodels for VLSI interconnect analysis. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 13, No. 10, 1257-1270 (1994).
213
Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 13, No. 6, 729-736 (1994).
214
Automatic Detection of Parallelism: A Grand Challenge for High-Performance Computing. (English)
IEEE Parallel and Distributed Technology 02, No.03, 37-47 (1994).
215
Moment-matching approximations for linear(ized) circuit analysis. (English)
Coughran, W. M. jun. (ed.) et al., Semiconductors. Part 1. Summer-School, Univ. Duluth, MN, USA, July 15 - August 9, 1991. Berlin: Springer. IMA Vol. Math. Appl. 58, 115-130 (1994).
216
Predicting circuit performance using circuit-level statistical timing analysis (English)
EDAC-ETC-EUROASIC, 332-337 (1994).
217
A gate-delay model for high-speed CMOS circuits (English)
DAC, 576-580 (1994).
218
OTTER: optimal termination of transmission lines excluding radiation (English)
DAC, 640-645 (1994).
219
io-port 70861611 Blume, William;
Eigenmann, Rudolf;
Faigin, Keith;
Grout, John;
Hoeflinger, Jay;
Padua, David A.;
Petersen, Paul;
Pottenger, William M.;
Rauchwerger, Lawrence;
Tu, Peng;
Weatherford, Stephen
Polaris: improving the effectiveness of parallelizing compilers (English)
LCPC, 141-154 (1994).
220
Result 201 to 220 of 250 total
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