@inbook {IOPORT.05961898,
    author       = {Carrillo, Snaider and Harkin, Jim and McDaid, Liam and Pande, Sandeep and Cawley, Seamus and Morgan, Fearghal},
    title        = {Adaptive routing strategies for large scale spiking neural network hardware implementations.},
    year         = {2011},
    booktitle    = {Artificial neural networks and machine learning -- ICANN 2011. 21st international conference on artificial neural networks, Espoo, Finland, June 14--17, 2011. Proceedings, Part I},
    isbn         = {978-3-642-21734-0},
    pages        = {77-84},
    publisher    = {Berlin: Springer},
    doi          = {10.1007/978-3-642-21735-7_10},
    abstract     = {Summary: This paper presents an adaptive Network-on-Chip (NoC) router, which forms part of an embedded mixed signal Spiking Neural Network (SNN) architecture called EMBRACE (Emulating Biologically-inspiRed ArChitectures in hardware). The novel adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoiding dropped router packets by adapting to router traffic congestion. The router also adapts to NoC traffic congestion or broken NoC connections (faults) by reconfiguring the routing topology to select an alternative route. Performance, power and area analysis of the proposed adaptive router using Synopsys Design Compiler (for TSMC 90nm CMOS technology) indicates a router throughput of 3.2Gbps on each of 5 available router channels, low router power consumption (1.716mW) and small router area ($0.056$ mm$^2$). Router adaptive behaviour in the presence of applied real-time traffic congestion has been demonstrated on a Virtex II Pro Xilinx FPGA for a 4x2 router array. Results indicate the feasibility of using the proposed adaptive NoC router within a scalable EMBRACE hardware SNN architecture.},
    identifier   = {05961898},
}