id: 06105151
dt: a
an: 06105151
au: Abburi, Kiran Kumar; Evani, Siva Subrahmanya; Thomas, Sajeev; Aprem, Anup
ti: Reusable and scalable verification environment for memory controllers.
so: Rahaman, Hafizur (ed.) et al., Progress in VLSI design and test. 16th
    international symposium, VDAT 2012, Shibpur, India, July 1‒4, 2012.
    Proceedings. Berlin: Springer (ISBN 978-3-642-31493-3/pbk). Lecture
    Notes in Computer Science 7373, 209-216 (2012).
py: 2012
pu: Berlin: Springer
la: EN
cc: 
ut: 
ci: 
li: doi:10.1007/978-3-642-31494-0_24
ab: Summary: With the increase in design complexity, verification times are
    growing significantly. Reuse of verification environment is an
    important means of reducing the verification effort. This paper address
    the problem of developing a reusable and a scalable verification
    environment for memory controllers. Though the architecture of
    different memory controllers varies significantly, they share a common
    transactional property. This property is exploited to develop a
    reusable verification environment. The proposed transactional
    verification environment coupled with the assertion based latency
    checkers achieve near cycle-accurate efficiency. The proposed
    verification environment is also scalable to verify memory controllers
    with multiple ports. We applied the above approach for the verification
    of three memory controllers, and results showed significant improvement
    in productivity and effectiveness.
rv: