id: 01967457
dt: j
an: 01967457
au: Sammut, K. M.; Jones, S. R.
ti: Arithmetic unit design for neural accelerators: Cost performance issues.
so: IEEE Trans. Comput. 44, No. 10, 1256-1260 (1995).
py: 1995
pu: Institute of Electrical and Electronics Engineers (IEEE), Washington, DC
la: EN
cc: 
ut: neural networks; linear array accelerators; instruction set measurements
ci: 
li: doi:10.1109/12.467702
ab: Summary: Arithmetic unit design is a key issue when supporting the
    computational requirements of neural networks. However, there is little
    quantitative evidence from the study of existing neural accelerators to
    help choose between arithmetic constructs. This paper presents an
    assesment of the cost-performance trade-offs between arithmetic
    constructs for linear neural accelerators.
rv: