id: 06105577
dt: a
an: 06105577
au: Briais, Sébastien; Caron, Stéphane; Cioranesco, Jean-Michel; Danger,
    Jean-Luc; Guilley, Sylvain; Jourdan, Jacques-Henri; Milchior, Arthur;
    Naccache, David; Porteboeuf, Thibault
ti: 3D hardware canaries.
so: Prouff, Emmanuel (ed.) et al., Cryptographic hardware and embedded systems
    - CHES 2012. 14th international workshop, Leuven, Belgium, September
    9‒12, 2012. Proceedings. Berlin: Springer (ISBN
    978-3-642-33026-1/pbk). Lecture Notes in Computer Science 7428, 1-22
    (2012).
py: 2012
pu: Berlin: Springer
la: EN
cc: 
ut: 
ci: 
li: doi:10.1007/978-3-642-33027-8_1
ab: Summary: 3D integration is a promising advanced manufacturing process
    offering a variety of new hardware security protection opportunities.
    This paper presents a way of securing 3D ICs using Hamiltonian paths as
    hardware integrity verification sensors. As 3D integration consists in
    the stacking of many metal layers, one can consider surrounding a
    security-sensitive circuit part by a wire cage. After exploring and
    comparing different cage construction strategies (and reporting
    preliminary implementation results on silicon), we introduce a
    “hardware canary”. The canary is a spatially distributed chain of
    functions $F _{i }$ positioned at the vertices of a 3D cage surrounding
    a protected circuit. A correct answer ($F _{n } \deg \cdots \deg F
    _{1})(m)$ to a challenge $m$ attests the canary’s integrity.
rv: