Result 1 to 20 of 145 total
FPGA-based Cherenkov ring recognition in nuclear and particle physics experiments. (English)
Koch, Andreas (ed.) et al., Reconfigurable computing: architectures, tools and applications. 7th international symposium, ARC 2011, Belfast, UK, March 23‒25, 2011. Proceedings. Berlin: Springer (ISBN 978-3-642-19474-0/pbk). Lecture Notes in Computer Science 6578, 169-180 (2011).
1
io-port 50037807 Liu, Ming;
Kuehn, Wolfgang;
Lange, S.;
Yang, Shuo;
Roskoss, J.;
Lu, Zhonghai;
Jantsch, Axel;
Wang, Qiang;
Xu, Hao;
Jin, Dapeng
A high-end reconfigurable computation platform for nuclear and particle physics experiments (English)
Computing in Science and Engineering 13, No. 2, 52-63 (2011).
2
Custom microcoded dynamic memory management for distributed on-chip memory organizations (English)
Embedded Systems Letters 3, No. 2, 66-69 (2011).
3
FPGA-based particle recognition in the HADES experiment (English)
IEEE Design & Test of Computers 28, No. 4, 48-57 (2011).
4
A low-overhead fault-aware deflection routing algorithm for 3D network-on-chip (English)
ISVLSI, 19-24 (2011).
5
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks (English)
NOCS, 57-64 (2011).
6
Realization and scalability of release and protected release consistency models in noc based systems (English)
DSD, 47-54 (2011).
7
Network-on-chip multicasting with low latency path setup (English)
VLSI-SoC, 290-295 (2011).
8
3-D integration and the limits of silicon computation (English)
VLSI-SoC, 343-348 (2011).
9
Modeling and analysis of Rayleigh fading channels using stochastic network calculus (English)
WCNC, 1056-1061 (2011).
10
Power-efficient tree-based multicast support for networks-on-chip (English)
ASP-DAC, 363-368 (2011).
11
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems (English)
ASP-DAC, 154-159 (2011).
12
FPGA-based cherenkov ring recognition in nuclear and particle physics experiments (English)
ARC, 169-180 (2011).
13
Concept and design of exhaustive-parallel search algorithm for network-on-chip (English)
SoCC, 150-155 (2011).
14
Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling (English)
ICCD, 445-446 (2011).
15
Buffer optimization in network-on-chip through flow regulation. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 12, 1973-1986 (2010).
16
Guest editorial: Special section on the ACM/IEEE symposium on networks-on-chip 2009. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 6, 853-854 (2010).
17
A worst case performance model for TDM virtual circuit in nocs. (English)
Ding, Chen (ed.) et al., Network and parallel computing. IFIP international conference, NPC 2010, Zhengzhou, China, September 13‒15, 2010. Proceedings. Berlin: Springer (ISBN 978-3-642-15671-7/pbk). Lecture Notes in Computer Science 6289, 452-461 (2010).
18
A worst case performance model for TDM virtual circuit in nocs (English)
NPC, 452-461 (2010).
19
Inter-process communication using pipes in FPGA-based adaptive computing (English)
ISVLSI, 80-85 (2010).
20
Result 1 to 20 of 145 total
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