05384009

j

05384009 Branger, Vincent Drach-Temam, Nathalie Data prefetching performances in superscalar processors. (Performances du pr\{\"\i}echargement de donn\{\"\i}ees dans les processeurs superscalaires.) RAIRO, Tech. Sci. Inf. 16, No. 5, 537-562 (1997). 1997 \'Editions HERMES, Paris EN C.1.2 F.1.2 C.3 high-performance processing superscalar processor sequential prefetching first-level cache second-level cache bus traffic Summary: Techniques used to reduce or tolerate large memory latencies are essential for achieving high processor performance. In this paper, data sequential prefetching techniques are more precisely investigated. We have studied the sequential prefetching performance on the first-level cache. This prefetching affects the superscalar processor performance by creating potential access conflicts to the first-level cache, by increasing the memory bus traffic and by not anticipating the processor need. Prefetching on the second-level cache overcomes these major drawbacks. Simulations show that sequential hardware prefetching on second-level cache outperforms prefetching on first-level cache, but these performances does not correspond to the algorithm efficiency. (Provider: Leibiger)