06067855

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06067855 Madan, Niti Buyuktosunoglu, Alper Bose, Pradip Annavaram, Murali Guarded power gating in a multi-core setting. Varbanescu, Ana Lucia (ed.) et al., Computer architecture. ISCA 2010 international workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19--23, 2010. Revised selected papers. Berlin: Springer (ISBN 978-3-642-24321-9/pbk). Lecture Notes in Computer Science 6161, 198-210 (2011). 2011 Berlin: Springer EN power gating queueing model multi-core guard mechanism

doi:10.1007/978-3-642-24322-6_17

Summary: Power gating is an increasingly important actuation knob in chip-level dynamic power management. In a multi-core setting, a key design issue in this context, is determining the right balance of gating at the unit-level (within a core) and at the core-level. Another issue is how to architect the predictive control associated with such gating, in order to ensure maximal power savings at minimal performance loss. We use an abstract, analytical modeling framework to understand and discuss the fundamental tradeoffs in such a design. We consider plausible ranges of software/hardware control latencies and workload characteristics to understand when and where it makes sense to disable one or both of the gating mechanisms (i.e. intra- and inter-core). The overall goal of this research is to devise predictive power gating algorithms in a multi-core setting, with built-in ``guard'' mechanisms to prevent negative outcomes: e.g. a net increase in power consumption or an unacceptable level of performance loss.