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A blocking reduction scheme for multiple slot cell scheduling in multicast switching systems. (English)
Sarbazi-Azad, Hamid (ed.) et al., Advances in computer science and engineering. 13th international CSI computer conference, CSICC 2008, Kish Island, Iran, March 9‒11, 2008. Revised selected papers. Berlin: Springer (ISBN 978-3-540-89984-6/pbk; 978-3-540-89985-3/ebook). Communications in Computer and Information Science 6, 168-175 (2008).
Summary: In this paper, we propose a multicast switch called BRMSCS switch consisted of shared memory, crossbar fabric and the scheduler BRMSCS (Blocking Reduction Multiple Slot Cell Scheduler). Our goals are to reduce the blocking situation in the scheduler and to guarantee free of Memory Access Conflict (MAC), that is, no more than two output ports would access the different cells which come from the same input port. We separate the BRMSCS switch into two parts: the data section and the control section. The header of each incoming cell is sent to the control section and scheduled by BRMSCS. To meeting our goals, the RRMSCS scheduler quickly inserts the address cell into scheduling table and fills the scheduling table as full as possible. The simulation results show that the BRMSCS scheduler can efficiently insert the address cell into the MAC free location of scheduling table and has the feature of reducing blocking.
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