@article {IOPORT.05783527,
    author       = {Jeng, Shiann-Shiun and Lin, Hsing-Chen and Chen, Chun-Chyuan and Chang, Shu-Ming},
    title        = {Hardware implementation and verification of FIR filter utilizing M-bit PDA.},
    year         = {2010},
    journal      = {Journal of Circuits, Systems, and Computers},
    volume       = {19},
    number       = {2},
    issn         = {0218-1266},
    pages        = {503-517},
    publisher    = {World Scientific, Singapore},
    doi          = {10.1142/S0218126610006207},
    abstract     = {Summary: An efficient architecture for a FPGA symmetry FIR filter is proposed that employs the M-bit parallel-distributed arithmetic (M-bit PDA). The partial product is pre-calculated and saved into the distributed ROM to eliminate a large amount of multiplications. Altera Stratix II EP2S60 is used as a target device to implement the M-bit PDA. The hardware implementation requires 936 adaptive look-up tables (ALUTs), 888 registers, 1 PLL, 40960 memory bits for the FIR filter implementation with the M-bit PDA (in this case $M = 2$). Additionally, the maximum clock rate for this implementation can be achieved up to 155.36 MHz. In comparison with the parallel multiplier/adder cell (MAC) and serial distributed arithmetic (SDA), the proposed architecture consumes a smaller area and operates with a higher speed due to omitting the multipliers.},
    identifier   = {05783527},
}