Result 1 to 20 from 87 total
Dynamic last-level cache allocation to reduce area and power overhead in directory coherence protocols. (English)
Kaklamanis, Christos (ed.) et al., Euro-Par 2012 parallel processing. 18th international conference, Euro-Par 2012, Rhodes Island, Greece, August 27‒31, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-32819-0/pbk). Lecture Notes in Computer Science 7484, 206-218 (2012).
1
Analysis of event-based, single-server nonstationary simulation responses using classical time-series models. (English)
Eur. J. Oper. Res. 218, No. 3, 676-686 (2012).
2
Evaluation of low-overhead organizations for the directory in future many-core CMPs. (English)
Guarracino, Mario R. (ed.) et al., Euro-Par 2010 parallel processing workshops. HeteroPar, HPCC, HiBB, CoreGrid, UCHPC, HPCF, PROPER, CCPI, VHPC. Ischia, Italy, August 31 ‒ September 3, 2010. Revised selected papers. Berlin: Springer (ISBN 978-3-642-21877-4/pbk). Lecture Notes in Computer Science 6586, 87-97 (2011).
3
Glocks: efficient support for highly-contended locks in many-core cmps (English)
IPDPS, 893-905 (2011).
4
The impact of non-coherent buffers on lazy hardware transactional memory systems (English)
IPDPS Workshops, 700-707 (2011).
5
Eager meets lazy: the impact of write-buffering on hardware transactional memory (English)
ICPP, 73-82 (2011).
6
ZEBRA: a data-centric, hybrid-policy hardware transactional memory design (English)
ICS, 53-62 (2011).
7
Characterizing the basic synchronization and communication operations in Dual Cell-based Blades through CellStats. (English)
J. Supercomput. 53, No. 2, 247-268 (2010).
8
Dealing with transient faults in the interconnection network of cmps at the cache coherence level (English)
IEEE Trans. Parallel Distrib. Syst. 21, No. 8, 1117-1131 (2010).
9
A direct coherence protocol for many-core chip multiprocessors (English)
IEEE Trans. Parallel Distrib. Syst. 21, No. 12, 1779-1792 (2010).
10
Heterogeneous interconnects for energy-efficient message management in cmps (English)
IEEE Trans. Computers 59, No. 1, 16-28 (2010).
11
Exploiting address compression and heterogeneous interconnects for efficient message management in tiled cmps (English)
Journal of Systems Architecture - Embedded Systems Design 56, No. 9, 429-441 (2010).
12
A scalable organization for distributed directories (English)
Journal of Systems Architecture - Embedded Systems Design 56, No. 2-3, 77-87 (2010).
13
Characterizing the basic synchronization and communication operations in dual cell-based blades through cellstats (English)
The Journal of Supercomputing 53, No. 2, 247-268 (2010).
14
An online and noninvasive technique for the condition monitoring of capacitors in boost converters (English)
IEEE T. Instrumentation and Measurement 59, No. 8, 2134-2143 (2010).
15
Simple experimental techniques to characterize capacitors in a wide range of frequencies and temperatures (English)
IEEE T. Instrumentation and Measurement 59, No. 5, 1258-1267 (2010).
16
Evaluation of low-overhead organizations for the directory in future many-core cmps (English)
Euro-Par Workshops, 87-97 (2010).
17
A G-line-based network for fast and efficient barrier synchronization in many-core cmps (English)
ICPP, 267-276 (2010).
18
Efficient and scalable barrier synchronization for many-core cmps (English)
Conf. Computing Frontiers, 73-74 (2010).
19
Characterizing energy consumption in hardware transactional memory systems (English)
SBAC-PAD, 9-16 (2010).
20
Result 1 to 20 from 87 total
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