@inbook {IOPORT.05854637,
    author       = {Yi, Wang},
    title        = {Multicore embedded systems: The timing problem and possible solutions.},
    year         = {2010},
    booktitle    = {Formal methods and software engineering. 12th international conference on formal engineering methods, ICFEM 2010, Shanghai, China, November 17--19, 2010. Proceedings},
    isbn         = {978-3-642-16900-7},
    pages        = {22-23},
    publisher    = {Berlin: Springer},
    doi          = {10.1007/978-3-642-16901-4_3},
    abstract     = {Summary: Today's processor chips contain often multiple CPUs i.e. processor cores each of which may support several hardware threads working in parallel. They are known as multicore or many-core processors. As a consequence of the broad introduction of multicore into computing, almost all software must exploit parallelism to make the most efficient use of on-chip resources including processor cores, caches and memory bandwidth. For embedded applications, it is predicted that multicores will be increasingly used in future embedded systems for high performance and low energy consumption. The major obstacle is that due to on-chip resource contention, the prediction of system performance, latencies, and resource utilization in multicore systems becomes a much harder task than that for single-core systems. With the current technology we may not predict and provide any guarantee on real-time properties of multicore software, which restricts seriously the use of multicores for embedded applications. In this talk, I will give an overview on the key challenges for software development on multicore architecture and briefly introduce the CoDeR-MP project at Uppsala to develop high-performance and predictable real-time software on multicore platforms. I will present the multicore timing analysis problem and our solutions proposed in a series of recent work. Technical details may be found in [LNYY10] on combining abstract interpretation and model checking for multicore WCET analysis, [GSYY09a] dealing with shared caches, [GSYY09b] on response time analysis for multicore systems, and [GSYY10] extending Layland and Liu's classical result [LL73] on rate monotonic scheduling for single-core systems to multicore systems.},
    identifier   = {05854637},
}