Result 1 to 20 of 63 total
Pass transistor operation modeling for nanoscale technologies. (English)
Ayala, José L. (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization, and simulation. 21st international workshop, PATMOS 2011, Madrid, Spain, September 26‒29, 2011. Proceedings. Berlin: Springer (ISBN 978-3-642-24153-6/pbk). Lecture Notes in Computer Science 6951, 53-62 (2011).
1
Applied chaos: Linearizing multibit $ΔΣ$ converters for telecom applications. (English)
J. Concr. Appl. Math. 9, No. 3, 197-204 (2011).
2
Pass transistor operation modeling for nanoscale technologies (English)
PATMOS, 53-62 (2011).
3
Design space exploration for FPGA-based multiprocessing systems (English)
ICECS, 1164-1167 (2010).
4
Real-time canny edge detection parallel implementation for fpgas (English)
ICECS, 499-502 (2010).
5
Input mapping algorithm for parallel transistor structures. (English)
Int. J. Circuit Theory Appl. 37, No. 7, 856-861 (2009).
6
Scalable register bypassing for FPGA-based processors (English)
Microprocessors and Microsystems - Embedded Hardware Design 33, No. 7-8, 441-452 (2009).
7
An integer linear programming model for mapping applications on hybrid systems (English)
IET Computers & Digital Techniques 3, No. 1, 33-42 (2009).
8
An application development framework for ARISE reconfigurable processors (English)
TRETS 2, No. 4 (2009).
9
ARISE machines: Extending processors with hybrid accelerators. (English)
Woods, Roger (ed.) et al., Reconfigurable computing: Architectures, tools and applications. 4th international workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings. Berlin: Springer (ISBN 978-3-540-78609-2/pbk). Lecture Notes in Computer Science 4943, 196-208 (2008).
10
Elimination of overhead operations in complex loop structures for embedded microprocessors. (English)
IEEE Trans. Comput. 57, No. 02, 200-214 (2008).
11
Elimination of overhead operations in complex loop structures for embedded microprocessors (English)
IEEE Trans. Computers 57, No. 2, 200-214 (2008).
12
Energy consumption estimation in embedded systems (English)
IEEE T. Instrumentation and Measurement 57, No. 4, 797-804 (2008).
13
ARISE machines: extending processors with hybrid accelerators (English)
ARC, 195-206 (2008).
14
Development of a customized processor architecture for accelerating genetic algorithms. (English)
Microprocess. Microsyst. 31, No. 5, 347-359 (2007).
15
Hardware support for arbitrarily complex loop structures in embedded applications. (English)
Comput. Res. Repos. 2007, Article No. 0710.4632 (2007).
16
Analysing the operation of the basic pass transistor structure. (English)
Int. J. Circuit Theory Appl. 35, No. 1, 1-15 (2007).
17
The ARISE reconfigurable instruction set extensions framework (English)
ICSAMOS, 153-160 (2007).
18
RFID based object localization system using ceiling cameras with particle filter (English)
FGCN (2), 37-42 (2007).
19
Implementation strategy and results of an energy-aware system-on-chip for 5 ghz WLAN applications. (English)
J. Low Power Electron. 2, No. 1, 18-26 (2006).
20
Result 1 to 20 of 63 total
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