<?xml version="1.0" encoding="utf-8" standalone="yes"?>
<item>
  <id>70542614</id>
  <dt>a</dt>
  <an>70542614</an>
  <augroup>
    <au>Wang, Chun-Chieh</au>
    <au>Liou, Jing-Jia</au>
    <au>Peng, Yen-Lin</au>
    <au>Huang, Chih-Tsun</au>
    <au>Wu, Cheng-Wen</au>
  </augroup>
  <ti>A BIST scheme for FPGA interconnect delay faults</ti>
  <so>VTS, 201-206 (2005).</so>
  <py>2005</py>
  <pu></pu>
  <lagroup>
    <la>EN</la>
  </lagroup>
  <ccgroup>
  </ccgroup>
  <utgroup>
  </utgroup>
  <cigroup>
  </cigroup>
  <ligroup>
    <li>http://doi.ieeecomputersociety.org/10.1109/VTS.2005.5</li>
  </ligroup>
</item>