id: 06114832
dt: j
an: 06114832
au: Cong, Jason; Gururaj, Karthik; Zhang, Peng; Zou, Yi
ti: Task-level data model for hardware synthesis based on concurrent
    collections.
so: J. Electr. Comput. Eng. 2012, Article ID 691864, 24 p. (2012).
py: 2012
pu: Hindawi Publishing Corporation, New York, NY
la: EN
cc: 
ut: 
ci: 
li: doi:10.1155/2012/691864
ab: Summary: The ever-increasing design complexity of modern digital systems
    makes it necessary to develop electronic system-level (ESL)
    methodologies with automation and optimization in the higher
    abstraction level. How the concurrency is modeled in the application
    specification plays a significant role in ESL design frameworks. The
    state-of-art concurrent specification models are not suitable for
    modeling task-level concurrent behavior for the hardware synthesis
    design flow. Based on the concurrent collection (CnC) model, which
    provides the maximum freedom of task rescheduling, we propose
    task-level data model (TLDM), targeted at the task-level optimization
    in hardware synthesis for data processing applications. Polyhedral
    models are embedded in TLDM for concise expression of task instances,
    array accesses, and dependencies. Examples are shown to illustrate the
    advantages of our TLDM specification compared to other widely used
    concurrency specifications.
rv: